V123S EVENT LINK MODULE

(a.k.a. SNS Design Manual - Integrated Control System - Timing and Synchronization System - Master Distribution System WBS 1.09.02.02 ).  Document Revision Status:Rev X. December 1, 2000 Document edit. \\C-adfile1\DATA\Kerner\SNS\V123S SNS Beam Sync Master\V123S revA2.htm using MS Word 2000 SR1
Kerner 06/20/2002
Modified BCF (beam clock fault) and added CIU (Clock in Use) status register 10/15/2001

Changed to MS Word editor – corrected typos

6/20/02 T.K. Changed default interrupt level request clear to ROAK for low level diagnostics from serial terminal connected to IOC vxWorks shell to prevent cascade interrupts.

Index

1.0 V123S SNS EVENT LINK ENCODER MODULE
1.1 System Introduction
1.1.1 Configuration
1.1.2 Purpose
1.1.3 Tolerances
1.1.4  System Operation
1.1.5 System Input Requirements
1.2 V123S SNS Event Link Encoder Module
1.2.1 V123S Event Encoder Input/Output Characteristics
1.2.1.1 V101 Event Input module input characteristics
1.2.2 V123S SNS Event Encoder Front Panel Displays
1.2.2.1 V101 Input Module Front Panel displays
1.2.3 Beam Synchronous System Module VMEbus Interface
1.2.3.1 Event Encoder Module Address Map
1.2.3.2 Event Encoder Module VMEbus Status/ID Message
1.2.3.3 Event Encoder Module Command Register
1.2.3.4 Event Encoder Module Interrupt Vector Register
1.2.3.5 Event Encoder Module Interrupt Level Register
1.2.3.6 Input Module Interrupt Vector Register
1.2.3.7 Event Encoder Module Event Trigger Input FIFO
2.0 System Drawing Numbers
2.1 V123S Module VMEbus Interface
2.2 V123S Logic EPLD 9402xxxx
2.2.1 VMEbus Interface
2.2.2 VMEbus Interface Registers
2.2.2.1 Revolution Counter (deleted)
2.2.3 VMEbus Interrupt
2.2.4 VMEbus Tri/State Data Bus
2.2.5 Beam Synchronous Circuits
2.2.5.1 Beam Synchronous Clock Failure
2.2.5.1.1 Crystal backup clock oscillator
2.2.5.2 Revolution Tick Pulse Failure
2.2.5.3 Beam Synchronous Event Slot Generator
2.2.5.4 Beam Synchronous Event Priority Circuit
2.2.5.5 Beam Synchronous Event Transmission
2.3 Input/Output Buffers
2.3.1 LED Drivers
2.3.2 V123S Beam Synchronous Module Backplane
2.3.3 Beam Clock and TEXT Extraction Tick Inputs
2.3.4 Beam Synchronous PECL Event Link Output
2.3.5 PECL Output and ECL Fanout Module
 
 
 

1.0 V123S SNS EVENT LINK ENCODER MODULE

1.1 System Introduction

The  V123S SNS Event Link Encoder (a.k.a. Beam Synchronous Master) generates ring LLRF beam synchronous timing events and informational events that are distributed site-wide via fiber optics, fan out hubs, and twisted wire pair. These events are transported on a carrier which is 16 times the ring LLRF frequency used by the accumulator ring cavities . This allows precise delivery of timing events to synchronize the LINAC, proton choppers, accumulator ring injection, accumulator ring extraction, 600 Hz neutron Fermi-chopper roller collimators, beam instrumentation triggers, and event driven controls around the ring, target, and experimental areas. Worst case jitter from source to destination with long cables has been measured at less than 1 ns peak to peak with the low cost PLL receiver. The V124S SNS Trigger Modules (a.k.a. Beam Synchronous Slaves) will apply custom programmable delays to these events. The V124S uses the ring LLRF beam synchronous clock to generate delays which are multiples of the clock period, plus an analog delay with 500 ps increments with over a 100 ns total adjustment range. Pulse widths, repetition counts, and timestamps are among the configurable parameters for each of the eight V124S outputs. Events may be logically or'd in a VME bus accessible lookup table. The FREV event synchronizes the DDS for the ring LLRF phase.  The DDS creates a 32 x FREV CW clock to drive the event link. The 60 Hz line DSP-PLL synchronizes a counter to develop PP, T0, TEXT. T0 (cycle start) then will be aligned with the average positive zero crossing of the AC line voltage. All subsequent fixed delay timing will be referenced to cycle start in increments and sub delays off the LLRF clock. Hence the event link system is LLRF source synchronous to allow machine tuning. Other timing events with no relation to cycle start can be put on the link asynchronously. The negative T0- crossing (cycle start minus) can be used to insert an optional cycle that can be easily turned on and off. The prepulse inputs are no longer required as cycle start will be advanced by at least 12 bit clocks to hold off on any asynchronous event activity that could preempt cycle start. This requires an internal counter in the V123S which will be added to the production boards along with an internal/external clock source output. Chained delays can be created by feeding back outputs to inputs.  Different events can have different delays, but the same event code cannot have different delays. In other words the delays associated with an event are not intended to be dynamically changed in real time unless a multi-user system is designed with on-board lookup tables that are swapped by user codes (synchronizing events). Changing delays in real time can be taxing on IOCs. Hardware triggered events are prioritized and distributed by the V123S along with up to 192  informational events from the IOC loaded via a FIFO. Informational events are transmitted with lower priority than hardware triggered events. Input trigger priority is position encoded on the V101 Event Input Modules. Event codes are assigned to these triggers in a translation table that is accessible from the VME bus. This allows easy re-prioritization of input triggers like a telephone switchboard without having to change any of the event codes in the large number of downstream receivers, and/or the OR’ing of events. The LINAC requires synchronization to the zero voltage crossing of the AC Power lines to within 100 microseconds, so the accumulator ring injection and extraction must be brought into coincidence by an event tracking the AC power zero crossing. This is accomplished by a DSP PLL with a long time constant, which filters the line frequency and keeps the cycle to cycle timing variation to well under 1 microsecond. This zero crossing pulse is delayed by a fixed number of clocks to develop cycle start (T0).  Cycle start (T0) is sampled by a 32 x LLRF clock, encoded with an event code and placed on  the event link. Injection timing then can be regulated so that the maximum time that the beam may expand in the machine after filling is kept well under 10 turns before extraction. The ring LLRF synthesizer will adopt a beam gap position generated by the FREV tick on a V124S (derived from dividing PLL recovered 16.92 MHz carrier clocks on the evnt link by 16 and synchronizing it with T0 cycle start). All V124S FREVs are phase aligned to the T0 cycle start (60 Hz zero line crossing supplied by the DSP PLL) delayed event transmitted on the event link by the V123S.  The V123S will drive all timing events synchronously from the 33.84 MHz (32x ring LLRF) RF clock using the first available clock with an asynchronous transfer protocol. The high inertia collimators will need little power to stay in phase with the slowly changing (33.84 MHz clock period jumping) DSP-PLL filtered AC line zero crossing events synchronous with the event link carrier derived from the ring LLRF RF clock.   The ring RF and hence the event link clock are in no way multiplied up from the AC power line frequency, only the event strings are initiated by T0 cycle start derived from the zero crossing. All of the SNS Event Link system boards are VME compatible with the exception of the fiberoptic chassis and the fan out modules. The V101 Input Modules take in 50 ohm triggers and priority encode those triggers for transmission to the V123S.  There are up to 4 V101s in the SNS event link system providing up to 16 triggers per V101. The V101 boards act as slave input modules to the V123S over a dedicated backplane. Each V101 module has 16 input triggers and its geographic position (slot) in the chassis incrementally determines the trigger values and priorities. The first V101 input module has the first 3 inputs capped off as these codes are used for T0+, T0- and, TEXT by the V123S.  The remaining 61 input triggers on the four V101s may be used for additional hardware triggers. After the higher priority hardware triggers there are 192 software triggers that may be loaded into the V123S FIFO. Software trigger codes range in value from 64 to 255, for a total of 192 software triggers. Software trigger values below 64 will be rejected by the V123s as these are reserved for hardware triggers. Trigger values are then assigned an event code by the SRAM lookup table. Therefore hardware event triggers are in priority order while event codes of any value may be assigned to these triggers including overlapping event codes for OR’ing triggers. This facilitates manual priority modifications by changing the location of hardware trigger inputs, while the lookup table can be modified to keep the same event code to prevent having to modify the event tables of the many downstream V124S modules. These event codes are then transmitted on the event link after framing and bi-phase mark encoding. The V124S Trigger modules are distributed around the complex and terminate the fanned out event link. These boards contain a low cost PLL receiver, bi-phase mark decoder, deframing logic, and event specific delays that form instrumentation triggers.The V123S, the V101, and the V124S and the interconnecting fiberoptics, receivers, monitor, fanouts and cable form what is called the event link system. Cycle start (T0 +,-) and Extraction (TEXT) are high priority real time events dedicated to the front panel of the V123S. They demarcate a critical timing period when both FIFO informational events and VME access to the lookup table are disabled to prevent preemption. As stated earlier for emphasis the software generated FIFO trigger values must be between 64 and 255 so as not to be confused with the higher priority hardware input triggers. To summarize; the position of the beam gap in the accumulator ring is a function of the LINAC timing which is supplied by the event link system.  Extraction events are aligned with this gap as well as collimator phase through the event link timing system. Cycle to cycle T0 timing changes are minimized by the filtering action of the DSP PLL. The LINAC is sensitive to the AC zero crossing so cycle start events are delayed from the filtered PLL crossings..

1.1.1 Configuration

The SNS event link encoder system is contained in a single VME chassis utilizing 5 dedicated slots. (1) V123S and (4) V101s. The slots are fixed by the dedicated P2 backplane. The event link carrier varies around 16.92 MHz, which is half the frequency of the 33.84 MHz RF clock supplied to the V123S derived from multiplying the SNS ring LLRF frequency by 32. The source of the T0 cycle start event is created by a direct digital synthesizer (DDS) VME board.  The event link is initiated as differential PECL, and distributed by the controls fiber optic system in a star configuration before being converted back to differential PECL by fanouts.  The fanouts connect to V124S PLL receivers where the clock and event codes are recovered.
 

1.1.2 Purpose

The low jitter recovered clocks are intended to provide precise timing information to instrumentation triggers and data acquisition systems used in experiments and for SNS monitoring and tuning purposes.  The T0 cycle start and TEXT, extraction events will have the highest priority and will be used by the extraction kicker, and as a reference for timing triggers and delayed timing triggers.  Other event link events will be sent on a priority basis, but may be delayed by the extraction event. Since this signal is fanned out in a star configuration, an event will arrive after a propagation delay at any location around the ring with nanosecond precision, and sub-nanosecond jitter.  Programmable delays are provided by the V124S distributed trigger modules synchronized to the T0 cycle start event, by programmable counts of the carrier clock and fine delays after low jitter PLL recovered carrier clock edges. Therefore the passage of any event around the complex can be signaled precisely with sub-nanosecond resolution.

1.1.3 Tolerances

The SNS WBS 192 conrtols timing plans estimate the required timing tolerances for various parts of the timing system. The granularity of the proposed timing is a function of the beam synchronous carrier for a 1.0 GeV machine, the granularity is 59 ns.  With offset delays in the trigger modules granularity can be reduced to 500 ps. The site wide jitter is expected to be well under 1 ns.  For up to date information go to the SNS web site at http://www.sns.gov/projectinfo

1.1.4  System Operation

The SNS Design Manual should be consulted for a general description of the accumulator ring, its functions and its terminology.  The timing section is located at
http://www.sns.gov/projectinfo/ics/192/1922/1922.html.  The SNS Controls documentation may be located at http://www.sns.gov/projectinfo. For the purposes of clarity, and to place the SNS event link system into proper context with accumulator ring operations; the event link terminology is described below in close proximity to associated SNS terminology, names, functions and operating parameters.  Informed readers may wish to skip this section.  The perspective is for the event link user or programmer, and is highly generalized to keep this document concise. The accumulator ring will deliver 20A pulses of protons at a 60 Hz rate and optionally at a 120 Hz rate into a mercury (Hg) target. The LINAC will deliver a chopped stream of protons at the ring revolution rate. A "fill and spill" cycle is 1.667 ms long, there are 10 of these cycles every 60 Hz cycle of which only two may contain protons. Depending on the energy of the machine several machine parameters will change. Some basic interrelated machine parameters for three proton injection energies are given in the table below.
 
 

248 meter ring

Mini-pulse length (ns)

Gap length (ns)

Revolution period (ns)

Revolution frequency (MHz)

RF frequency (MHz)

Beta

Event Granularity (ns)

842MeV

655.1

324

973.4

1.027,323

32.874,340

84.984 %

60.84

1.0GeV

630.3

315

945.4

1.057,767

33.848,545

87.503 %

59.09

1.3GeV

607.4

304

911.2

1.097,502

35.120,070

90.790 %

56.95

The RF clock is 32X the revolution rate. Because the revolution rate is so high due to the small ring diameter, it is impractical to transmit a revolution event, which would eat up most of the system bandwidth. In lieu of a 1 MHz revolution event, the T0 cycle start event will be sent to fix the phase of the FREV in the V124s once per machine cycle. The V124s will then divide the carrier clock down by 16. The DSP-PLL will guarantee a fixed number of clocks between T0 and TEXT at a 120 Hz rate to accomodate the planned extra accumulation cycle. Any adjustment in the number of clocks is made at the beginning of the machine cycle (T0 cycle start). V124 Trigger modules will generate the FREV tick by synchronizing a counter running on the event link PLL recovered carrier clock. The counters are synchronized by the T0 events.  All devices will be synchronized to this reconstructed FREV revolution tick using the recovered PLL carrier clock. The T0, TEXT events are generated by counting 32x ring LLRF clocks and synchronized by the AC line zero crossing DSP-PLL.

· 


The positive and negative 60Hz line sync events will "wander" with respect to the RF clock phase. Since they are quantized by a 32x multiple of the ring LLRF they will appear to jump back and forth by a single clock cycle period of 59 ns every 120 Hz. The injection of the new protons to the accumulated protons must happen in phase to leave an extraction gap opening of at least 280 ns to accommodate the rise time of the extraction kicker. If the extraction kicker were not to rise to full field in the 315 ns gap, the beam would be sprayed in all directions contributing to excessive radiation losses. The protons accumulate over about 1060 revolutions until they reach a very high space charge density at 20 Amps, at this maximum density the beam will expand beyond the confines of the ring if it is not extracted immediately. The event link system must coordinate the injection choppers, extraction kicker, and roller collimator events. TEXT(Time extract) is used to fire the kicker in the beam gap. T0 is used to identify the start of the Linac cycle triggered by the 60 Hz line sync signal coincident with one of the line AC zero crossings. Cycle start is transmitted 12-bit times ahead of the event link transmitted event to ensure that there will be no preemption by an earlier event.  Magnetic fields bend and (RF) electric fields constrain the protons in a C shaped bunch within the ring. The LINAC will produce protons, anywhere from 842 MeV  to 1.3 GeV depending on design and setting, in a chopped stream to maintain a gap in the accumulator ring for extraction purposes. The SNS event link is a serial data transmission medium where an 8-bit event code is framed with one start bit, a parity bit, and two stop bits.  This 12-bit frame is modulated to create a modified Manchester NRZ data stream using bi-phase mark encoding.  The encoding is necessary to transfer the signal with minimal loss over impedance controlled transformer coupled twisted wire pair cables and fiber optic transmitters and receiver components.  This modulation method has the effect of creating a 16.92 MHz clock stream when no data is being transmitted or when the link is said to be "idle ones", and a 8.46 MHz clock when transmitting "all zeroes".  Regardless of the data content, a 16.92 MHz carrier clock is recovered from the data stream on the event link by a clock recovery Phase Lock Loop (PLL).  The first zero transmitted after power on will correct the PLL clock phase. The PLL also functions to minimize jitter created by dispersion effects of the modulated data in the transmission cables.  The event link is fanned out around the SNS complex in a star configuration.  The SNS event link transmission cables are a combination of shielded twisted pair twinaxial cables for local fan out and distribution, and fiber optic cables for longer hauls.  The distributed V124S Trigger modules at the ends of the fanned out event link cables will decode the events and produce timing pulses with programmable delay counters running off the clock recovered from the event link.  Prioritized "trigger codes" are translated in a SRAM lookup table into 8-bit "event codes" which are encoded into bi-phase mark and transmitted on the event link. T0 cycle start and TEXT triggers are a programmable number of clock cycles apart counted off a multiple of the ring LLRF.  The storage accumulator ring gap is produced by the LINAC mini-pulses using timing derived by dividing down the 16.92 MHz carrier by 16 in the V124S modules.

ECL fannouts were designed to handle the 16.92 MHz event link carrier with adaptive cable equalizers to handle dispersion induced by long cables. A low cost PLL recovery circuit was designed, built and tested in the V124S trigger modules to handle the full range of machine operating energies with minimal jitter.

1.1.5 System Input Requirements

The V123S requires a quality input RF clock to meet SNS event link specifications. Specifically the RF clock must be a continuous low noise +10 dBm sinewave without step-wise phase transitions or gaps. This continuous carrier wave (CCW) clock must be present at all times that the event link system is in use, and must be phase coherent. These CCW conditions must be valid even when the accumulator ring has no beam or is not operational. Any Frequency changes or sweeps should not exceed about 100kHz/sec. The V123S requires a T0 cycle start event which must always be available. The event link encoder chassis requires UPS AC power or holdover power within the VME chassis specs. The V123S event encoder system will not be responsible for providing a synthetic ring LLRF clock or synthetic input triggers of any kind to substitute for the unannounced or unplanned loss of inputs. The V123S will switch to a fixed internal clock automatically when the ring LLRF clock is interrupted or falls out of the frequency window such that the RF clock loss VME interrupt and the event link itself will remain operational. Hence the ring LLRF clock substitution will only occur after an input failure causing a momentary output carrier loss which is not the fault or responsibility of the event link system. This clock substitution occurs within 1 ms after a clock failure to aid in operations such as a beam dump, but this is not fast enough to prevent the PLL receivers in the V124 from loosing lock, and when they do it will take about 5 mS to regain lock. So the ring LLRF must be CCW and should never be lost. When planned interruptions are necessary, the V123S can be switched to internal clock via VME control, in advance of the loss. This switching does not preserve frequency or phase information. The step change in frequency and phase may cause the trigger modules to loose lock for up to 5 ms. Should RF switching be required without step wise transient induced loss of  lock, then a Switched Reference PLL (SRPLL) should be introduced between the ring LLRF frequency source and the V123S.  If a temporary lock loss condition is acceptable, the time when it is switched should be carefully selected to coincide with machine operations in standby or during non critical timing periods. The event link encoder system was not designed for dynamic clock substitution without introducing transients.

Below are the SNS event link encoder module block diagrams.

figure 1.1.1

figure 1.1.2
figure 1.1.3figure 1.1.4

At a SNS beamsync hub location, the fiber optic transmission is converted to differential ECL. The beam extraction time is approximately 60 extractions/second. The V123S event link encoder requires a 2 x clock that is two times the idle one event link carrier. For example, the event link encoder receives a 33.84 MHz clock and derives a 16.92 MHz event link carrier. The 2x clock is provided by multiplying the ring LLRF by 32.  The extraction tick TEXT generates the extraction event code which is encoded and transmitted with minimal latency synchronized with the RF clock. A 33.84 MHz crystal backup clock oscillator will provide an event link output when the RFclock is not available ( no beam ) for system testing and development purposes. This is helpful during construction, maintenance and commissioning. A control register bit can override automatic switching which is the default condition. The most important event transmitted by the event link encoder is the extraction event. The extraction tick must be in phase with the beam gap. The gap must be large enough to accomodate the rise time of the extraction kicker and any granularity of the event link system. The extraction tick event code is synchronized to the RF extraction tick input during SNS operation. While operating on the crystal backup clock oscillator, the extraction tick event code will not be in phase with the LLRF. WARNING: As the SNS RF system initializes, the V123S module instantly selects the RF clock if that clock falls within a preset frequency window about the internal reference clock oscillator. The following the T0 cycle start input will jam synchronize the V123S revolution tick dividers. These two actions will cause an event carrier phase change, and a jump in the position of the revolution tick provided by the V124S modules.  Event link receivers will indicate parity and loss of lock errors when switching between internal and external clock modes. Manually switching into a dead LLRF will cause immediate link carrier loss and lock loss on all downstream receivers.  The event link event codes are transmitted using a serial modified Manchester code (bi-phase-mark). Bi-phase mark guarantees a signal level transition at each cell edge, rather than at the center as is done in the true Manchester code (bi-phase). A "one" is defined as a level transition in the cell center, while no center transition is a "zero". There are roughly 28,200 LLRF clock periods between T0 and TEXT. At full bandwidth 2,300 events could be transmitted in that time. In a single revolution period there are always 16 bit cells which can contain a single 12-bit framed and encoded event aligned with the gap for Text. During idle periods, the event link contains continuous bi-phase-mark "ones" (16.92 MHz square wave) transmission, with a single extraction event once per machine cycle. Even parity is selected so that idle "ones" bi-phase cells always start with a positive, rising edge, transition at the V123S module output. A single event code transmission, requires approximately 709 ns, shown in figure 1.1.5. Example:
Bi-phase mark 8-bit data with 1 start (0), 8 data, 1 parity (even), and 2 stop (1) bits
0xF0 data, most significant bit first convention. Idle (1) during no data transmission results in a 16.92 MHz square wave.
Dashed lines mark the edges of each bit cell.
The bi-phase mark 1 has a transition in the center of the bit cell, the zero has none.  Transitions at the edges of each bit cell are required. Even parity with even (12-bit) code words restores the phase of the idle ones to a high value at the beginning of the bit cell.  Odd parity would have the effect of alternating the high value from the beginning to the end of each bit cell during idle 1 transmissions after each word is transmitted.
 

S is the Start bit
P is the Parity bit
S1 is the first Stop bit
S2 is the second Stop bit
 
 

figure 1.1.5

 
 

figure 1.1.6

This figure shows data pattern 0xF4 data.  The even parity bit restores the start bit data phase as seen after stop bit 2.  Odd parity would alternate the phase of the stop bits and start bits.


 
 

figure 1.1.7

This figure shows the effect of odd parity on data pattern 0xF0 on the phase of the stop bits and idle ones.

The next start bit would have opposite polarity.

1.2 V123S SNS Event Link Encoder Module

The V123S SNS event link encoder module features:
 

1.2.1 V123S Event Encoder Input/Output Characteristics

Four front panel inputs to the V123S are Pre Pulse (PP), T0 ("tee zero"), TEXT ("tee extract"), and RF clock. There is one front panel twinaxial BNC output for the event link encoder. One (1) single-ended ring LLRF clock (33.84 MHz) SMA input terminated into 50 ohms. The input expects a CCW 10 dBm sine wave, 1V peak, or 2V peak-to-peak signal level into the 50 ohm load. This input can also be a PECL squarewave. The rising edge of the the ring LLRF clock should nearly coincide with the rising edge of the extraction tick to guarantee stable setup and hold time due to an internal propagation delay in the V123S. The RF input is isolated from digital ground via an input transformer.

1.2.1.1 V101 Event Input module input characteristics

NOTE: The Beamsync event encoding system uses four V101 input modules derived from V101 event link input modules.  The V101 modules are intended to have a modified priority EPLD to reduce the 13 clock delay (1.3 ms in V101 modules) to 2-3 clock cycles to allow more rapid event triggering.  In contrast to the synchronous V123 RHIC beam synchronous system, where events are transmitted in event slots, the V123S transmits on the first available clock edge asynchronously.

NOTE: External trigger channels 0x00 through 0x03 in the first V101 module are not used and are capped off. Trigger 0x01 is the extraction tick event assigned to the dedicated front panel input, 0x02 is the T0 , and 0x03 is the PP dedicated V123S front panel inputs.  Trigger 0x00 is considered a null event by default and is used for unassigned events.  Caution must be exercised not to exercise these four inputs via software triggers. The V101 driver software should be designed to mask these software inputs.

1.2.2 V123S SNS Event Encoder Front Panel Displays

V123S SNS Event Encoder display characteristics from front panel top to bottom are:

1.2.2.1 V101 Input Module Front Panel displays

V101 Input Module display characteristics from front panel top to bottom are:

1.2.3 Beam Synchronous System Module VMEbus Interface

The beam synchronous event encoder modules are VMEbus slaves. The VMEbus interface and formfactor for V123S and V101 module characteristics:

NOTE: The V123S module address decode logic selects both the V123S and V101 modules. A beam synchronous encoder always requires a 4K-byte block of A16 memory, even if there are less than 16 V101 modules.

1.2.3.1 Event Encoder Module Address Map

The beam synchronous event encoder module base address is set in a 4-bit jumper patch where J[1..4] = A[15..12]. The simple decoding used in VMEbus A16 interface requires that the base address be a multiple of 0x1000, and that 0x1000 (4K) bytes are reserved for the event encoder system.   The revolution counter bytes at BASE + 4C, 4D, 4E,  4F are not supported since this is not a D32 interface, and reading all the bytes concurrently is not possible.  The rollover of one byte before the second byte is read will result in a bad reading.
 This file contains the SNS V123S addressing. Addresses are different from V123 due to various modifications. No revolution counter, longer VMEID string, etc.  Note 1: PROM on odd bytes only, even bytes are "." Note 2: SWR represents base address dip switches.  event encoder/input module A16 addressing
|-----------|-----------|-----------|-----------|
|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
|-----------|-----------|-----------|-----------|
|----SWR----| 0| ENC_ADDR (up to 16 V123S base addresses)
               | 0  0  0  X  X  X  X  X  X  X  1|R/- BYTE status/ID PROM odd
               | 0  0  0  X  X  X  X  X  X  X  0|R/- BYTE status/ID PROM even "."
               | 0  1  0  0  0  0  0  0  0  0  1|R/W BYTE CSRA - occurrence status
               | 0  1  0  0  0  0  0  0  0  1  1|R/W BYTE V123S int vector reg
               | 0  1  0  0  0  0  0  0  1  0  1|R/W BYTE interrupt level reg
               | 0  1  0  0  0  0  0  0  1  1  1|R/W BYTE V101 interrupt vector
               | 0  1  0  0  0  0  0  1  0  0  1|R/W BYTE FIFO
               | 0  1  0  0  0  0  0  1  1  0  1|R/W BYTE error register
               | 0  1  0  0  0  0  0  1  1  1  1|R/- BYTE real time status
               | 1  0  0  X  X  X  X  X  X  X  X|R/W WORD event code translation SRAM
|----SWR----| 1| INP_ADDR | (up to 4 V101s)
               |--CHANNEL--| 16-channel codes from P2 backplane
               | 0  X  X  X  X  X  X|R/- BYTE VME status/id
               | 1  0  0  0  0  0  0|R/W HI-BYTE channel enable
               | 1  0  0  0  0  0  1|R/W LO-BYTE channel enable
               | 1  0  0  0  0  1  0|R/W HI-BYTE interrupt enable
               | 1  0  0  0  0  1  1|R/W LO-BYTE interrupt enable
               | 1  0  0  0  1  0  0|-/W HI-BYTE event trigger
               | 1  0  0  0  1  0  1|-/W LO-BYTE event trigger
               | 1  0  0  0  1  1  0|R/- HI-BYTE lost event
               | 1  0  0  0  1  1  1|R/- LO-BYTE lost event
               | 1  0  0  0  1  1  1|BYTE unused
               | 1  0  0  0  1  1  1|R/- BYTE interrupt vector
               | 1  0  0  0  1  1  1|BYTE unused
               | 1  0  0  0  1  1  1|R/W BYTE interrupt level% %----------------------------------------------------------------------------%

%LAST_V101 = the numeric value of the last V101 trigger channel%
constant LAST_V101 = 63; %four V101 modules%

|-----------+-----------+-----------+-----------|
|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
|-----------+-----------+-----------+-----------|
|----SWR----|                                   |
| X| X| X| X|                                   |BASE_ADDRESS
            | 0  0  0  0  X  X  X  X  X  X  X  X| V123S VME status/ID
            | 0  0  1  0  0  0  X  X  X  X  X  X| V123S registers
            | 0  1  0  0  X  X  X  X  X  X  X  X| V123S translation
            | 1  0  0  0  0  X  X  X  X  X  X  X| First V101
            | 1  0  0  0  1  X  X  X  X  X  X  X| Second V101
            | 1  0  0  1  0  X  X  X  X  X  X  X| Third V101
            | 1  0  0  1  1  X  X  X  X  X  X  X| Fourth V101

V123S MODULE

BYTE FIELD DEFINITIONS at each address:
STATUS ID from BASE + (000 to 0FF)
                          ---------------------------------
BASE + 000 STATUS/ID      | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | Even addresses ASCII "." 2E
                          ---------------------------------
                                          "
                          ---------------------------------
BASE + 0FF STATUS/ID      | X | X | X | X | X | X | X | X | Odd addresses ASCI characters
                          ---------------------------------

                          ---------------------------------
BASE + 201 COMMAND_REG A  |RFB|ACS|FF | 4 |A/K|X/R|INT|ONL| occurrence status
                          +---+---+---+---+---+---+---+---+
BASE + 203 INT_VEC_REG    | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
                          +---+---+---+---+---+---+---+---+
BASE + 205 INT_LEV_REG    | X | X | X | X | X | 2 | 1 | 0 |
                          +---+---+---+---+---+---+---+---+
BASE + 207 INP_INT_VEC    | 7 | 6 | 5 | 4 | X | X | X | X |
                          +---+---+---+---+---+---+---+---+
BASE + 209 FIFO           | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
                          +---+---+---+---+---+---+---+---+
BASE + 20D ERROR_REG      |FIE|ITE|ETE|VME|EXE|PPE|T0E|TEE| occurrence status
                          +---+---+---+---+---+---+---+---+
BASE + 20F STATUS- RT     |BCF| 0 |FFR| 0 | 0 |CIU|P-T|FE | real time status
                          +---+---+---+---+---+---+---+---+
                          +---+---+---+---+---+---+---+---+
BASE + 400 EVENT TABLE    | X | X | X | X | X | X | X | X |
                          +---+---+---+---+---+---+---+---+
                                          "
                          +---+---+---+---+---+---+---+---+
BASE + 4FF EVENT TABLE    | X | X | X | X | X | X | X | X |
                          +---+---+---+---+---+---+---+---+

FIRST V101 MODULE         +---+---+---+---+---+---+---+---+
BASE + 800 STATUS/ID      | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 |
                          +---+---+---+---+---+---+---+---+
                                          "
                          +---+---+---+---+---+---+---+---+
BASE + 83F STATUS/ID      | X | X | X | X | X | X | X | X |
                          +---+---+---+---+---+---+---+---+
                          +---+---+---+---+---+---+---+---+
BASE + 840 CHAN_ENA_HI    | F | E | D | C | B | A | 9 | 8 |
                          +---+---+---+---+---+---+---+---+
BASE + 841 CHAN_ENA_LO    | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
                          +---+---+---+---+---+---+---+---+
BASE + 842 INT_ENA_HI     | F | E | D | C | B | A | 9 | 8 |
                          +---+---+---+---+---+---+---+---+
BASE + 843 INT_ENA_LO     | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
                          +---+---+---+---+---+---+---+---+
BASE + 844 EVENT_TRG_HI   | F | E | D | C | B | A | 9 | 8 |
                          +---+---+---+---+---+---+---+---+
BASE + 845 EVENT_TRG_LO   | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
                          +---+---+---+---+---+---+---+---+
BASE + 846 LOST_EVENT_HI  | F | E | D | C | B | A | 9 | 8 |
                          +---+---+---+---+---+---+---+---+
BASE + 847 LOST_EVENT_LO  | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
                          +---+---+---+---+---+---+---+---+

BASE + 848 N/A            |   |   |   |   |   |   |   |   |
                          +---+---+---+---+---+---+---+---+
BASE + 849 STATUS ID      | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
                          +---+---+---+---+---+---+---+---+
BASE + 84A N/A            |   |   |   |   |   |   |   |   |
                          +---+---+---+---+---+---+---+---+
BASE + 84B IRQ LEVEL      | X | X | X | X | X | 2 | 1 | 0 |
                          +---+---+---+---+---+---+---+---+

SECOND V101 MODULE ( subsequent modules duplicate the table above ) BASE + 880
THIRD V101 MODULE BASE + 900
FOURTH V101 MODULE BASE + 980

˚ ˚ ˚
SIXTEENTH V101 MODULE BASE + F80

Abbreviations:
INT - Interrupt Enable, interrupts disabled(default)
ONL - On Line / Off line(default) - After power-up OFF-Line default prevents FIFO events from being transmitted to allow proper SRAM table initialization. After table setup and input trigger enabling, this bit is placed on line.
A/K - RORA / ROAK(default) Interrupt (release on register access / release on IACK )
BCF - Beam Clock Fault - real time external 32 x Frev clock (LLRF) out of frequency window if high. ( see next)
RFB - RF clock Bad - occurence, external 32 x Frev clock was bad sometime before the last clear operation. Useful in detecting intermittents by timestamping on an interupt.
ACS - Automatic Clock Switching. Power up default is disabled requiring manual switching using X/R CRA[2]. If set, and the 32 x Frev external clock leaves the frequency window, it will cause a switch to the internal clock. If the external 32 x Frev clock reenters the frequency window, then it will switch back to the 32 x Frev external clock automatically. Switching is not phase or frequency coherent so downstream PLLs will temporarily unlock which is expected and normal. Loss of the 32 x Frev external clock should be avoided with beam in the machine. ACS is provided to allow a synthetic clock to drive the event link when the LLRF is off-line with no beam in the machine.
X/R - Xtal / RF Clock Control, when high Xtal clock is selected, when low RF clock is selected. Overriden if ACS is set.
FFR - FIFO Full - real time, FIFO is full when this bit reads high. (see next)
FF - FIFO Full - occurence, FIFO was full some time before last clear operation. Indicates an application problem where events were lost.
FE - FIFO empty - real time, FIFO is empty when this bit reads high. A normal situation.
CIU - Clock in Use - real time status bit 1 = Internal, 0 = External 32xFrev. This bit status will be distributed to all users and the safety system before beam can be enabled.  Essential status when "ACS" automatic clock switching is enabled, or when manual internal clock is selected.
P-T - Pre pulse to T extract interval - real time, the interval is active when this bit reads high. Only high priority events are allowed in this time to prevent low priority events from triggering first and holding off a high priority extraction event. No FIFO events allowed during this time. No VME SRAM table access allowed during this time.
ERROR_REG:
DCIRE7 - FIFO Input Data Value Rejected X < 64 (0x40) error.
DCIRE6 - Input Timing error - T0, PP, TEXT during BPM busy
DCIRE5 - External Trigger Bus value < 3 (0x03) OR > 63 (0x3F) error
DCIRE4 - VME access - RAM - double clock input rate error
DCIRE3 - V101 External Take_data double clock input rate error
DCIRE2 - Pre Pulse double clock input rate error
DCIRE1 - T0 double clock input rate error
DCIRE0 - TEXT double clock input rate error

COMMAND_REG A:
CRA7 RF clock fail (H=True)
CRA3 RORA/ROAK H/L
CRA4
CRA5 FIFO Full (H=True)
CRA6 Automatic Clock Switching (ON/OFF H/L)
Control Register bit definitions:
CRA0 on line ONL (ON/OFF H/L)
CRA1 interrupt enable INT (ON/OFF H/L)
CRA2 XTL/RF clock H/L

STATUS- RT:
SRA0 - FIFO_EMPTY
SRA1 - PP-TEXT
SRA2
SRA3
SRA4
SRA5 - FIFO_FULL
SRA6
SRA7 - RFCKFAIL

SECOND V101 MODULE BASE + 880
THIRD V101 MODULE BASE + 900
FOURTH V101 MODULE BASE + 980
SIXTEENTH V101 MODULE BASE + F80

                          Event Encoder Module Registers

1.2.3.2 Event Encoder Module VMEbus Status/ID Message

Located at the BASE_ADDRESS is the 64-byte, read only, VME board status/ID message. The message contains module type, serial number, and revision information. All even bytes contain an ASCII ".", odd bytes contain the information. The registers are byte read only. The following links to the status/ID message format.

1.2.3.3 V123S Event Encoder Module Command Register

A VME interface register that sets the operational mode of the V123S and shows occurrence status. This includes putting the module on line, enabling interrupts, selecting input clock source, defining the interrupt release, and setting the automatic clock switching mode. Two status bits are provided for FIFO full occurrence, and RF clock failure occurrence. The interrupt enable bit is set to allow the module to generate a VMEbus interrupt on FIFO full, RF clock failure, and , PP, T0, TEXT  input double trigger errors.
(see section 2.2.2 for register details)

1.2.3.4 V123S Event Encoder Module Interrupt Vector Register

The interrupt vector register is located at BASE_ADDRESS + 0x203. The register contains the V123S event encoder module interrupt vector sent to the front end computer during an interrupt cycle. The register is byte read-write. As a minimum, this vector must be unique for any of the seven IRQ levels, and optionally for any IRQ level, and is used by the IOC to identify which interrupter has requested service on any of the seven IRQ levels. IRQ levels are priority based with IRQ7 having the highest and IRQ1 having the lowest priority. This register’s contents are determined by the system level integrator for use by the interrupt handler in the IOC.

1.2.3.5 V123S Event Encoder Module Interrupt Request Level Register

The V123S interrupt request (IRQ) level register is located at BASE_ADDRESS + 0x205. The register determines interrupt request level (IRQ7 to IRQ1) and optionally a setting for IRQ level 0 will disable interrupt requests. The register contains only three active read-write bits. These  3 bits are the least significant bits in the byte (2 .. 0). The register is byte read-write.

1.2.3.6 V101 Input Module Interrupt Vector Register

All V101 input modules get their most significant nibble (bits 7..4) for their interrupt vectors from the V123S register at 0x207 .  This ensures that all V101s for any V123 master are set the same to avoid conflict. The least significant nibble of the interrupt vector (bits 3..0) is obtained from the geographic slot number hardwired in the dedicated backplane.  The least significant nibble is fixed as 0 in the leftmost V101 slot and as 3 in the rightmost V101 slot. The most significant nibble is transmitted to the V101 input modules in parallel via the dedicated V123S Beam Synchronous Module Backplane. The most significant nibble can be written or read as a byte with don’t care bits in the least significant nibble. The least significant nibble of a V101 input module interrupt vector (3 .. 0) is obtained from its position on the V123S Beam Synchronous Module Backplane.

1.2.3.7 V123S Event Encoder Module Event Trigger Input FIFO

The event trigger FIFO input is located at BASE + 0x209 and is byte read and write.  The last word clocked out of the FIFO may be read from this register.  This allows a loop-back test of this register.  Only codes equal to 0x40 or higher {64 decimal} will be written to this FIFO because the 64 higher priority V101 input module triggers are reserved for these codes.  The FIFO configuration is 256 X 8.  Byte strings may be entered at the VMEbus rate.  If the module is placed off-line this FIFO can be filled resulting in a FIFO full error.  Bytes written to a full FIFO are lost.  Byte strings may be queued in the FIFO for batch mode release when the module is placed on-line.  It is important to note that these triggers are also translated into event codes through the SRAM lookup table just like the input triggers. FFR indicates the FIFO status. It is highly unlikely that the FIFO will ever fill.

 

1.2.3.8 V101 Input Trigger Module Status ID and IRQ Level registers

The Status ID is defined by the V123S most significant nibble in base + 0x205 and the least significant nibble comes from the dedicated backplane. This value (byte read only) can be read from each V101 base + 0x849.  The IRQ level register is at base + 0x84B and is byte read/write.  The default IRQ level = 0, which is disabled.  Each V101 must have its IRQ levels set in order to generate interrupts.  V101s occupy 2048 bytes in A16 space.  The Nth V101 address can be computed from the first V101 module addresses in the above table by adding N*(0x800)

 

2.0 System Drawing Numbers

Reference:
9402xxxx Module Assembly V123S Beam Synchronous Encoder Module
9402xxxx Schematic Diagram V123S Beam Synchronous Encoder Module
9402xxxx PWB Drilling V123S Beam Synchronous Encoder Module
9402xxxx PWB Assembly V123S Beam Synchronous Encoder Module
9402xxxx Front Panel Drill & Screen V123S Beam Synchronous Encoder Module
9402xxxx EPLD V123S Beam Synchronous Encoder Module
 
9402xxxx PWB Assembly Beam Synchronous Module Backplane
9402xxxx PWB Drilling Beam Synchronous Module Backplane
9402xxxx Schematic Diagram Beam Synchronous Module Backplane
 
 
NOTE: Use the V101 description for the V101 module: Link to the V101 description

2.1 V123S Module VMEbus Interface

VMEbus connectors P1 and P2 are shown on drawing 9402xxxx. The P1 input signals; A[15..1], AM[5..0], DS[1..0]*, AS*, WRITE*, SYSCLK, and SYSRST* are buffered by 74ABT244 non-inverting octal bus buffers U1, U3, U4, and U5. The bi-directional data bus signals; D[31..0] are buffered by bi-directional octal buffers 74ABT245 U6, U7, U8, and U22. Module DTACK* reply and interrupt requests IRQ[7..1]* are buffered by open collector octal buffer 74LS641DW U10. IACKIN* and IACKOUT* are not buffered as these signals are part of a point-to-point daisy chain interrupt priority system. The high-order bits of the A16 address, A[15..12], are compared to jumper register JP[1..4] in EPLD U2, an EPF10K10. The jumper pull-up resistors are provided. The comparison is done in the EPLD as there was logic and pins available after the primary design was completed. The VMEbus peripheral devices are addressed using memory mapped I/O; the address compare represents the V123S module A16 memory space. As a VMEbus slave, this module cannot become a bus master. Therefore, BG[0..3]IN* is connected to BG[0..3]OUT* in the printed wiring traces. VMEbus P2B D[31..16]: The 32-bit VMEbus data extension (D16-D32) is NOT SUPPORTED by the V123S beam synchronous encoder module, and the address extension (A23-A31) is not used.

2.2 V123S Logic EPLD 9402xxxx Link to Altera Block Diagram

EPLD 9402xxxx U2 is an Altera EPF10K10QC208-3. The Altera EPM10K10 contains 576 logic elements of which 80% are used by this design , connected via an X-Y matrix. All 3 embedded array blocks (EAB) are used for the FIFO, STATUS/ID, and event code translation table, and are programmed via an external EPROM U24, an EPC1441PC8. This EPLD contains all the V123S logic. The other integrated circuits are input/output buffers. EPLD 9402xxxx U2 is driven by two clock inputs; the 33.84 MHz crystal backup clock oscillator global input, and the 33.84 MHz RF beam synchronous clock. The crystal backup clock oscillator is used for:

The beam synchronous clock (RF clock)  is used to generate the beam synchronous event link. The beam synchronous clock frequency window discriminator determines which clock source to use for the beam synchronous event link clock (CLOCK_IN) RF or crystal. If the beam synchronous clock is within the window limits 15/14 and 13/14 of the crystal clock,  it becomes CLOCK_OUT, if not the crystal backup clock oscillator is used. CLOCK_OUT is looped back external to the EPLD to become global CLOCK_IN.

2.2.1 VMEbus Interface

The buffered VMEbus signals are input to EPLD U2. The VMEbus interface is controlled by a 3-bit shift register SR[2..0]. The shift register is held reset until released by DS0* or DS1*, which indicates a VMEbus byte transfer start. Both the VMEbus and the event generator use the same EPLD EAB SRAM array which is not dual ported. Therefore, a VMEbus cycle can't occur when an event trigger translation is in progress. The lowest priority trigger is reserved for a dummy VME event cycle. This ensures that VME access does not interrupt important events, and that the VME cycle does not gain access concurrently with real event encoding. This asynchronous approach by adding a cycle is different than the cycle stealing approach of the RHIC V123 with deterministic event slots. The interface is A16 D08(OE). Access to the functions are via read/write registers. A table is provided in this document for register addresses and register contents.
4 jumpers select 1 of 16 base addresses for these boards left justified in A16 space. Hex ( 0 .. F). These are normally selected by the address selection requirements for use in a given chassis. We will use a default jumper value of Hex 1. This address was used in the test and development scripts. The first byte of the VMEID will then appear at 0xffff1000 on a MVME162 FEC.
 

2.2.2 VMEbus Interface Registers

The following registers are located in EPLD U2:

o